Choon Keong Ong, Chee‐Chong Teo, Lip Pin Yeo
Abstract
The purpose of this project was to study the impact of release input, lot dispatch and lot batching policies on the mean and variance of cycle time in the semiconductor back-end facility.
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The purpose of this project was to study the impact of release input, lot dispatch and lot batching policies on the mean and variance of cycle time in the semiconductor back-end facility.
Key concepts: Scheduling (production processes), Manufacturing engineering, Semiconductor device fabrication, Engineering, Computer science, Industrial engineering, Operations management, Electrical engineering