Design of a fully differential current buffer (FDCB) based on a new common mode feedforward (CMFF) based common mode separation technique

In this paper, a new approach, the advantages of which are simplicity, low voltage and power and high common mode currents rejection, is presented for implementing of FDCB. CMFF is one of the best choices to insert a fully differential current substractors (FDCS) into the FDCB's structure resulting in high CMRR without using negative feedback. The proposed circuit profits from current-mode and fully differential signal processing. Simulation results provided by the Hspice software in 180nm CMOS TSMC process clearly proves the advantages of this design. Furthermore, the layout is done by Cadence, the area of which is 53*25.2(um)2. In the post layout simulations, the CMRR and the positive and negative PSRR are 58.19 dB, 117.1 dB and 147.8 dB, respectively. Input and output resistance and their bandwidth are 49.26 Ω, 2.4 MHz, 634.9 kΩ and 2.19 MHz, respectively. The proposed circuit under supply voltages of ±0.7 V consumes low power of 152.5 uW. The results of the corner cases and Monte Carlo simulations indicate that the performance of proposed circuit is less sensitive to fabrication process and temperature.