2002•Unpublished venueRequires access

PowerPC processors

A. Marsala, Basel Kanawati

Open publisher page 4 citations

Abstract

In October of 1991, IBM, Apple, and Motorola formed an alliance to produce a new microprocessor family named the PowerPC. Less than two years later, the alliance has produced the first chip of the PowerPC family, the MPC601. The paper analyzes the PowerPC 6xx family, with an emphasis on the architecture of the MPC6O1 chip. The 601's Reduced Instruction Set Computer (RISC) architecture is examined, including the three parallel execution units (integer unit, branch unit, and floating point unit), the instruction unit, the memory management unit, and the system interface. In addition, the software environments for the PowerPC are discussed. Finally, conclusions about the chip are drawn and an outlook on the future of the PowerPC family is made.>

About this research paper

What this paper is about

In October of 1991, IBM, Apple, and Motorola formed an alliance to produce a new microprocessor family named the PowerPC. Less than two years later, the alliance has produced the first chip of the PowerPC family, the MPC601. The paper analyzes the PowerPC 6xx family, with an emphasis on the architecture of the MPC6O1 chip. The 601's Reduced Instruction Set Computer (RISC) architecture is examined, including the three parallel execution units (integer unit, branch unit, and floating point unit), the instruction unit, the memory management unit, and the system interface. In addition, the software environments for the PowerPC are discussed. Finally, conclusions about the chip are drawn and an outlook on the future of the PowerPC family is made.>

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OpenAlex reports 4 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

In October of 1991, IBM, Apple, and Motorola formed an alliance to produce a new microprocessor family named the PowerPC. Less than two years later, the alliance has produced the first chip of the PowerPC family, the MPC601. The paper analyzes the PowerPC 6xx family, with an emphasis on the architecture of the MPC6O1 chip. The 601's Reduced Instruction Set Computer (RISC) architecture is examined, including the three parallel execution units (integer unit, branch unit, and floating point unit), the instruction unit, the memory management unit, and the system interface. In addition, the software environments for the PowerPC are discussed. Finally, conclusions about the chip are drawn and an outlook on the future of the PowerPC family is made.>

Key concepts: PowerPC, IBM, Operating system, Reduced instruction set computing, Computer science, Microprocessor, Interface (matter), Embedded system

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