Power Optimization of Configurable Logic Block in FPGA via Controlling Logic State of Virtual Ground Voltage

In this article, power optimization is investigated in Configurable Logic Block (CLB) of Field Programmable Gate Array (FPGA) for 65nm technology via controlling Virtual Ground Voltage (V ssv ) state that follows Power-Gated standard.Initially different Configurable Logic Block are designed through the logic gates and then expanded via adding Look Up Table circuit (LUT) in inputs; afterwards, the samples of Configurable Logic blocks are investigated in two logic states of Virtual Ground Voltage =0 and Virtual Ground Voltage =1 regarding the power dissipation; whereas 100µs is time reference for simulation of time controller of Virtual Ground Voltage function.First Configurable Logic Block are kept at logic state of Virtual Ground Voltage =1(power gated) for 10µs out of 100µs and remaining time at logic state of Virtual Ground Voltage =0 (power not gated); then the simulation test is repeated up to 50µs in 5 steps for each Configurable Logic Block sample.Finally the result shows that reduction being at logic state of Virtual Ground Voltage =0 in a constant time period has linear effect on decreasing average power.With the Configurable Logic Block in operation for 50% of the total time in Virtual Ground Voltage =1 logic state, the average power reduces up to 49% in the best case scenario.Meanwhile the Configurable Logic Block can still preserve its logic state.