Design and Synthesis of Reduced Delay BCD

Arithmetic and memory address computation are performed using adder operations. Hence, design of adders form an important subset of electronic chip design functionality. Performance of BCD adders is to be considered with gate count, area, delay, power consumption. A new BCD adder design is attempted here to reduce the delay and thereby increasing the speed of response. BCD adder design is considered with respect to high speed addition requirement including multi operand addition, multiplication and division. The new architecture supports 64 bit and 128 bit operands and reduces the delay by adding parallelism.