1998•IEICE Transactions on ElectronicsRequires access

A Real-Time MPEG2 Encoding and Decoding Architecture with a Dual-Issue RISC Processor

S. Uramoto, K. Tsuchihashi, E. Holmann, Akira Yamada, Takeshi Yoshida, Takeshi Matsumura

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Key concepts: Decoding methods, Reduced instruction set computing, Computer science, Dual (grammatical number), Encoding (memory), Architecture, Computer architecture, Embedded system

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