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1996•ITC-CSCC :International Technical Conference on Circuits Systems, Computers and CommunicationsRequires access

New Speedup Method of Lock Up Time in the PLL Frequency Synthesizer

Yasuaki Sumi, Shigeki Obote, Kazutoshi Tsuda, Kouichi Syoubu, Yutaka Fukui

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Key concepts: Phase-locked loop, Speedup, Lock (firearm), Computer science, Parallel computing, Jitter, Telecommunications, Engineering

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New Speedup Method of Lock Up Time in the PLL Frequency Synthesizer — Research Paper | ScholarLens