2003•DR-NTU (Nanyang Technological University)Requires access
Design and optimization of a low-voltage CMOS circuit for portable applications
Chee Chong. Chan
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Abstract
In this project, a literature study on the existing low-voltage low-power CMOS static logic circuits is first performed. This report proposes a modified square root carry-select adder with high speed, small area and minimized power dissipation at a low operating voltage of 1.5V. This is achieved by replacing the dual ripple-carry adders with a carry skip adder for zero-carry in.