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Design of a low-voltage CMOS analogue multiplier

Leow, Hee Boon.

Abstract

The objective of this project is to design a low-voltage analogue multiplier operating on a 1.3V voltage supply and its' 3-dB bandwidth is expected to be about 100 KHz. This multiplier should be able to operate with the input signals of the 1.2V voltage swing and expect an output voltage swing of more than lOmV. Its' main application is primarily used for voice signal processing.

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Available abstract

Key concepts: CMOS, Low voltage, Multiplier (economics), Electrical engineering, Analog multiplier, Voltage multiplier, Electronic engineering, Voltage