Design of Three Stage CMOS Comparator in 90nm Technology

A topology of a CMOS comparator circuitry employing three stages is proposed. In the design of Analog-to-Digital Converter (ADC), speed limiting element is the comparator. As comparator is one of the blocks that limits the speed of the converter, its optimization is crucial and important. This paper describes the schematic design of a three stage CMOS comparator. The main objective of the proposed project is to design a three stage CMOS comparator to achieve lower power dissipation and a lower offset voltage, with high-speed operation. Test structures of the comparator are designed using GPDK 90nm Technology with Cadence environment. Simulation results are obtained and it shows that the proposed design can work under 1.8V supply, with an offset voltage of 200mV, and a low power dissipation of 102.3µW. Thus, an innovative circuit technique is implemented to overcome these limitations.