Introduction of Depletion Stopper for Reduction of JFET Resistance for 4H-SiC Trench MOSFET

This paper investigates thereduction of parasitic resistance (JFET resistance) betweenthe p-well and the grounded p-type gate-oxide protection layer (BPW)of a trench-gate SiC-MOSFET. Forming a deeptrench is a way to reducethe JFET resistance, but this consequently leads to high electric field at thebottom oxide. In order to improve the trade-off between the specific on-resistance (Ron,sp) and the maximum bottom oxide electric field (Eox), wenewly developed a trench-gate SiC-MOSFET with an n-type region, named DepletionStopper (DS), formed under the entire p-welllayer. As aresult of fabrication, Ron,sp of the trench-gate SiC-MOSFET with DS is70 % lower than that without DS at a trench depth (dt) of about 1.5 mm. The dtof the trench-gate SiC-MOSFET with DS can be designed 25 % shallower than thatwithout DS at a Ron,sp of about 3.0 mWcm2.Therefore, it can reduce the JFET resistance and allow to shrinkthe trench depth. Optimizing the parametersof DS, the structure having DS is an effective means of reducing the JFETresistance, while reducing Eox by minimizing the depth of the trench.