ScholarLens Back to search
2002•ITC-CSCC :International Technical Conference on Circuits Systems, Computers and CommunicationsRequires access

Transistor Sizing Considering Slew Information to Reduce Glitch Power in CMOS Digital Circuit Design

Hyung-Woo Lee, Juho Kim

Open publisher page 8 citations

Abstract

This record does not include an abstract. Use the full-text link above if available.

About this research paper

What this paper is about

An abstract is not available in the OpenAlex record for this paper.

Why it matters

OpenAlex reports 8 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Key concepts: Glitch, CMOS, Computer science, Electronic engineering, Slew rate, Sizing, Transistor, Power (physics)

Related papers

Related paper 1Related paper 2Related paper 3
Back to paper searchBrowse research topicsOriginal source
Transistor Sizing Considering Slew Information to Reduce Glitch Power in CMOS Digital Circuit Design — Research Paper | ScholarLens