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2003•ITC-CSCC :International Technical Conference on Circuits Systems, Computers and CommunicationsRequires access

Design of A 12-bit 100 MHz CMOS Digital-to-Analog Converter

Ju Sang Lee, Gyu Hyun Kim, Ri A Ju, Sang Dae Yu

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Abstract

In this paper, a 12-bit 100 MHz CMOS current steering digital-to-analog converter is designed. In the digital-to-analog converter, a driver circuit using a dynamic latch is implemented to obtain low glitch, a thermometer decoder is used for low DNL errors, guaranteed monotonicity, reduced glitching noise and a threshold voltage-compensated method current source is used. The digital-to-analog converter is designed with 0.35 μm CMOS technology at 3.3 V power supply and simulated by HSPICE.

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What this paper is about

In this paper, a 12-bit 100 MHz CMOS current steering digital-to-analog converter is designed. In the digital-to-analog converter, a driver circuit using a dynamic latch is implemented to obtain low glitch, a thermometer decoder is used for low DNL errors, guaranteed monotonicity, reduced glitching noise and a threshold voltage-compensated method current source is used. The digital-to-analog converter is designed with 0.35 μm CMOS technology at 3.3 V power supply and simulated by HSPICE.

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Available abstract

In this paper, a 12-bit 100 MHz CMOS current steering digital-to-analog converter is designed. In the digital-to-analog converter, a driver circuit using a dynamic latch is implemented to obtain low glitch, a thermometer decoder is used for low DNL errors, guaranteed monotonicity, reduced glitching noise and a threshold voltage-compensated method current source is used. The digital-to-analog converter is designed with 0.35 μm CMOS technology at 3.3 V power supply and simulated by HSPICE.

Key concepts: CMOS, Glitch, Digital-to-analog converter, Analog-to-digital converter, Electronic engineering, Flash ADC, Electrical engineering, 12-bit

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