Analysis and optimization under crosstalk and variability in deep sub-micron vlsi circuits

With very large scale integrated (VLSI) circuit fabrication entering the deep sub-micron era, devices are scaled down to finer geometries, clocks are run at higher frequencies, and more functionality is integrated into one chip. All these bring a great promise of system-on-a-chip, but also introduce challenging new issues in the design process. As a result of the increasing frequency and density, coupling effects or crosstalk between neighboring wires are increased. These effects can cause functionality and timing failures in a circuit. The dynamic power consumption in charging or discharging coupling capacitances is timing dependent, and contributes significantly to a circuit's power consumption. In addition, manufacturing process variations (e.g. VT, Le), and environmental variations (e.g. Vdd, Temperature) contribute to uncertainties that deeply impact the timing characteristics of a circuit. This variability makes timing verification, and consequently, timing driven circuit optimization extremely difficult. Although worst case analyses for circuit optimization are simpler, they are not desirable since they severely over-constrain the optimization problem, and result in designs that have excessive penalties in terms of area or power consumption. In this research, we investigate the essential problems of timing verification, power estimation, and circuit (area or power) optimization under crosstalk and variability. We show that a circuit optimization problem under constraints on the maximal induced noise on each wire is equivalent to a fixpoint computation problem in a complete lattice. An optimal algorithm to solving this problem is developed, and is extended to handle variations. Under explicit timing constraints, we solve this problem in a Lagrangian Relaxation framework. We present a timing yield driven circuit optimization algorithm that considers variability and is based on statistical timing methodologies. Approaches to fast and approximation error aware statistical timing analysis are developed that also consider effects due to coupling as well as variability. Multiple input switching effects are considered for improved timing accuracy. We signify the importance of the timing dependence of dynamic power consumption in coupling capacitances, and develop an algorithm for accurate and efficient power estimation. Experimental results validate our approaches, and are promising.