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2009•ITC-CSCC :International Technical Conference on Circuits Systems, Computers and CommunicationsRequires access

A radix-8/4/2 FFT processor for OFDM systems

Jung-min Park, Young‐Jin Kim, Hyon-Soo Lee

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Abstract

In this paper, we propose an efficient variable-length radix-8/4/2 FFT architecture for OFDM systems. The proposed FFT processor is based on radix-8 FFT algorithm. For the limitation of FFT length, if it cannot run radix-8 FFT algorithm at the last stage then it computes radix-4 or radix-2 FFT algorithm. Furthermore, proposed FFT architecture use shared-memory to minimize and simplify hardware. We use efficient In-place memory access method to maintain conflict-free data access and minimize memory size. The proposed FFT architecture can be applied to variable FFT lengths including 64, 128, 256, 512, 1024, 2048, 4096 and 8192 points which cover all the required FFT lengths used in 802.11a, 802.16a, DAB, DVB-T, VDSL and ADSL.

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What this paper is about

In this paper, we propose an efficient variable-length radix-8/4/2 FFT architecture for OFDM systems. The proposed FFT processor is based on radix-8 FFT algorithm. For the limitation of FFT length, if it cannot run radix-8 FFT algorithm at the last stage then it computes radix-4 or radix-2 FFT algorithm. Furthermore, proposed FFT architecture use shared-memory to minimize and simplify hardware. We use efficient In-place memory access method to maintain conflict-free data access and minimize memory size. The proposed FFT architecture can be applied to variable FFT lengths including 64, 128, 256, 512, 1024, 2048, 4096 and 8192 points which cover all the required FFT lengths used in 802.11a, 802.16a, DAB, DVB-T, VDSL and ADSL.

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Available abstract

In this paper, we propose an efficient variable-length radix-8/4/2 FFT architecture for OFDM systems. The proposed FFT processor is based on radix-8 FFT algorithm. For the limitation of FFT length, if it cannot run radix-8 FFT algorithm at the last stage then it computes radix-4 or radix-2 FFT algorithm. Furthermore, proposed FFT architecture use shared-memory to minimize and simplify hardware. We use efficient In-place memory access method to maintain conflict-free data access and minimize memory size. The proposed FFT architecture can be applied to variable FFT lengths including 64, 128, 256, 512, 1024, 2048, 4096 and 8192 points which cover all the required FFT lengths used in 802.11a, 802.16a, DAB, DVB-T, VDSL and ADSL.

Key concepts: Fast Fourier transform, Split-radix FFT algorithm, Computer science, Asymmetric digital subscriber line, Twiddle factor, Prime-factor FFT algorithm, Digital subscriber line, Parallel computing

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