State Increment Method of Asynchronous Circuit

This paper presents an asynchronous circuit analysis method, the state increment method. A state increment is introduced that takes the clock rising and falling edges as logic variables and into logic operations. The method avoids the checking of the clock state when writing the state transition table. It is therefore simpler, less error prone, and more efficient in analyzing an asynchronous circuit. It can also convert the asynchronous circuit into its synchronous equivalent.