New Irregular Augmented Shuffle Multistage Interconnection Network

The design of a suitable interconnection network for inter-processor communication is one of the key issues of the system performance. In this study, a new irregular interconnection network NIASN (New Irregular Augmented Shuffle Network) has been proposed. Proposed NIASN achieve a significant improvement over some other popular MINs in terms of permutation passibility and cost- effectiveness. In the era of parallel processing the multistage interconnection networks are frequently projected as connections in multiprocessor systems to interconnect several processors with several memory modules or processors. A multistage network is capable of connecting an arbitrary input terminal to an arbitrary output terminal (3). In general a typical MIN consists of more than one stage of small interconnection networks called switching elements (SEs)(2,7). The stage and number of switching elements may vary from network to network. There are many parameters like cost, and permutation passable that are deciding factor for the whole system performance (6). In this paper, an irregular class of multistage interconnection network named NIASN is designed and analyzed. This paper is organized as follows: Section II describes the construction procedure of proposed network. Section III provides a brief introduction to cost effectiveness and its analysis. Section IV describes the permutation passability analysis of some MINs. Finally, conclusions are given in Section V.