Implementation of 32-Bit Wave Pipelining Sparse Tree Adders

In this paper, we propose 32-bit parallel prefix sparse tree adder. In general N-bit adders like Ripple carry adders(slow adders compare to other adders), and carry lookahead adders(area consuming adders) are used in earlier days. But now the most of industries are using parallel prefix adders because of their advantages compare to other adder, The prefix sparse tree adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. We simulate and synthesis different types of 32-bit sparse tree adders using Xilinx ISE tool, By using these synthesis results, We noted the performanceparameters like number of LUT’s and delay. We compare these three adders interms of LUT’s represents area) and delay values..