Safety Computatiions in Integrated Circuits

In order to ensure the safety of soware-based railway control systems, MATRA TRANSPORT has developped at the beginning of the eighties an informational redundancy technique associating arithmetic coding ad signature checking, with the adequate environment interfaces (generally fail-safe devices). Compared to traditional redundancy, the processor has the advantage of a rigorous mathematical safety demonstration, independant of the reliability of the underlying hardware, but there is an important cost to pay in terms of execution speed. One of the (strongly) desired evolutions of our systems is to have a unique centralized wayslde equipment, the immediate corollary beeing the decentralization of inputs/outputs. In order to reach this goal, a new generation has been designed, replacing the software code calculutions and the discrete numeric components used in coded input acquisition / coded auput command by ASICs. Our experience shows that it is possible to perform safe corrputations in an ASIC, and even that in some cases ASICs are wwre adapted to the safety constraints than somare computations.