An Ultra-Wideband Receiver Front-end

The needs for short range and fine resolution communication systems has intrigued researchers to replace wire-line communications systems with ultra-wideband communications systems. The Ultra-wideband radio technology introduces significant advantages for short-range communications systems. This technology operates in a wide bandwidth, which allows for Gigabit data rates over short distances. Due to the low complexity of the ultra-wideband system and low transmit power, it benefits from low DC power consumption. However, with growing demands for wireless communications systems, more challenging requirements are faced with the ultra-wideband communications systems. Since ultra-wideband covers a wide range of frequency, it exhibits challenges in the design of building blocks, receiver front-end in particular. The scope of this thesis is to design a novel and innovative RF front-end receiver for ultra-wideband transceivers using CMOS technology. A T-coil network can be implemented as a high order filter for bandwidth extension. This technique is incorporated into the design of the input matching and output peaking networks of a low-noise amplifier. The intrinsic capacitances within the transistors are exploited as a part of the wideband structure to extend the bandwidth. Using the proposed topology, a wideband low-noise amplifier with a bandwidth of 3−8 GHz, a maximum gain of 16.4 dB and noise figure of 2.9 dB (min) is achieved. The total power consumption of the wideband low-noise amplifier from the 1.8 V power supply is 3.9 mW. The prototype is fabricated in 0.18 μm CMOS technology. Furthermore, a two-stage down-conversion architecture for 3.1−8 GHz ultra-wideband receiver front-end is designed which uses a local oscillator frequency equal to half the input frequency. A single stage low power single-to-differential low noise amplifier is designed to eliminate the need for an off-chip balun and increases the integrity level of the frontend receiver. Consecutively, the RF frequency is down-converted in two steps based on 1 half-RF architecture to produce baseband signal. The proposed architecture has many advantages such as linearity and good port-to-port isolation. The proposed technique is implemented in 0.18 μm CMOS technology which achieves a conversion gain ranges from 36.1−32.4 dB and noise figure of 5.4−8.3 dB across the bandwidth.