AIGaAs/GaAs HBT Logic for Static Memory Application

In this work we evaluate the performance of a new gate topology that gives large logic swings and high noise margin, at low power dissipation. The measured noise margin (43% of 3 V logic swing) and transfer characteristics for a hybrid inverter using an Al- GaAs/GaAs heterojunction bipolar transistor are presented along with simulated data for an integrated device. These simulations lead to a modified structure demonstrating substantially improved transient re- sponse and reduced power dissipation (23 ps and 2.1 mW) while main- taining a large noise margin (45% of 3 v logic swing). Its performance is compared with emitter coupled logic (ECL).