6T- SRAM for Low Power Consumption

In the current technology demand for Static Random Access Memory (SRAM) is increasing drastically due to its usage in almost all system on chip high performance processors and VLSI circuits. In this paper we present a six transistor (6T) Static Random Access Memory cell for low power applications. The proposed design has strong read static noise margin (SNM) and strong write ability of logic one is achieved, which is problematic in an SE-SRAM cell. The impact of process variation on the different failure mechanism in SRAM cell is analyzed. A 32 bit SRAM with proposed and standard 6T bit cells is simulated and evaluated for read SNM, write ability and power. In the proposed SRAM architecture based on 6T cell using 0.18um technology reduced leakage power dissipation compared to standard 6T SRAM.