Desynchronization of digital circuits

In theory asynchronous circuits hold some great advantages over synchronous circuits, they are more robust towards variations in the environment such as temperature changes and voltage drops. At the same time asynchronous circuits can be compared to fine grained clock gating of a synchronous circuits, which if the circuit has idle time could save power. Finally asynchronous circuits does not have a finite clock cycle it consists of multiple local clocks generated by handshake controls, this should introduce a reduction in current spikes and EMI noise. The use of asynchronous circuits today is limited to small scale prototyping and research experiments, the reason is that the computer aided design tools does not support the design flow for asynchronous design. Also designing asynchronous circuits is not so straight forward as designing synchronous ones, and especially debugging can be some what of a challenge. This Thesis focuses on developing a method of desynchronization, to change a synchronous circuit into the asynchronous equivalent only by removing the clock, and by substitution of flipflops with latches. The first task is to implement some basic components in VHDL and create behavioral versions, the second task is to create synthesizeable versions of these components. Third task is to test on some examples and to establish a design flow for the synthesis and test of desynchronous circuits.