DESIGN OF 64 BIT ERROR TOLERANT ADDER

Adders are the core element of complex arithmetic operations like addition, multiplication, division, exponentiation etc. In most of these systems adder lies in the critical path that affects the overall speed of the system. This project introduces the design of low power error tolerant adder which acquires less area with the lowest transistor count. Enhanced performance of the proposed Error Tolerant adder in terms of power makes it suitable for portable image processing applications where minimum percentage of error is tolerable. The low power error tolerant adder circuit design and the simulation have been carried out on T a n n e r EDA tool. The result shows that t h e proposed low power error tolerant adder is an efficient adder cell with less MOS transistor count that reduces the high power consumption and it considerably increases the speed.