Energy Efficiency Enhancement in Mobile Processor Cache Memory Design Using Emerging Nonvolatile Memory

Motivation Memory hierarchy design creates an illusion of a high-speed and large-capacity memory by utilizing different types of memories. L1 cache implemented by SRAM reduces the latency between CPU and main memory. However, as technology scaling, increasing leakage power for SRAM has posed challenges to circuit and architecture designs in future memory hierarchy. In the mean time, emerging memory technologies, such as STT-RAM, PCM and RRAM, are being explored as potential alternatives to existing memories in future computing systems. Such nonvolatile memory technology, combining the speed of SRAM, the density of DRAM and the non-volatility of flash memory, offers a tremendous opportunity for low-power solution in mobile processors.