DESIGN OF PULSE TRIGGERED FLIP-FLOP AND ANALYSIS OF AVERAGE POWER USING PASS TRANSISTOR LOGIC

Among the various building blocks in digital designs, the most complex and power consuming is the flip-flop. Proper selection of flip-flops is necessary in order to satisfy low power and high performance circuit. In this paper, a novel low power PT-FF design is presented. The paper investigation of conventional and proposed pulse Triggered flip-flop is done with comparisons of average power which claims that proposed design is suitable for low power applications. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. The average power consumption and number of transistor count should be reduced by proposed pulse triggered flip-flop design. It will be having much reduced power and area when compared to the other two designs. The performance of the proposed design has been evaluated using Tanner EDA in 130 nm CMOS process technology.