Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding

The MD5 (Message Digest 5) hash algorithm is useful for verifying the correctness and integrity of an arbitrary message, but the data dependency in the critical path in its iterations causes a huge computational delay and reduces the system's throughput. This paper describes three-stage and four-stage pipeline MD5 implementations (3SMD5 and 4SMD5) on FPGA, which removes the data dependency in the iteration by the data forwarding method, and breaks that single step computation into 3 or 4 pipeline stages. The four-stage pipeline with both the keys and the constant table located in the BRAM could operate at the highest frequency, because its critical paths are shortened to one adder and some data movements at all stages. The processing of two messages in the alternative form enabled the four-stage pipeline architecture to achieve a higher frequency and throughput than related fine-grained pipelining architectures. Thus, the implementations achieve a good trade-off between the hardware size and the throughput.