Bias Dependence of Gate Oxide Degradation of 90 nm CMOS Transistors Under 60 MeV Proton Irradiation

This paper reports on the radiation response of 90 nm CMOS transistors to a high fluence (3times1012p/cm2) of ~60 MeV protons. A pronounced dependence on the gate bias VGS during the exposure has been noted for the n-channel devices: while no degradation of the input and output characteristics is found for VGS=0 V and a modest degradation for floating gate conditions, a catastrophic failure can be observed when a positive gate bias of 1.2 V is applied. This behavior is found for devices with a physical gate oxide thickness of 1.5 and 2 nm and appears to be more pronounced for larger area transistors. As will be shown, the breakdown site is connected with either the source-to-gate or drain-to-gate junction, whereby the latter leads to a complete loss of functionality of the transistors. However, some of the biased nMOSFETs survive the high-energy proton exposure without degradation. A model will be proposed, explaining the gate oxide breakdown in terms of pre-existing defect sites at the source or drain junctions which develop into breakdown sites under biased irradiation