Analysis of ACPR performance for memoryless predistorter considering power amplifier memory effects
Hyunchul Ku, J.S. Kenney
Abstract
Hyunchul Ku, J.S. Kenney
Abstract
Memory effects in a power amplifier (PA) limit the improvement of performance for predistortion linearizers based on memoryless look-up table (LUT) or model-based architectures. This paper investigates degradation of the adjacent channel power ratio (ACPR) improvement for a PA with memoryless predistortion linearizer with respect to the memory effects. Using the input and output complex envelope signals of PA, the ACPR degradation due to memory effects is analytically extracted. A 170 W PEP LDMOS PA is measured and its ACPR performance degradation due to memory effects is analyzed using a memoryless predistortion linearizer.
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Memory effects in a power amplifier (PA) limit the improvement of performance for predistortion linearizers based on memoryless look-up table (LUT) or model-based architectures. This paper investigates degradation of the adjacent channel power ratio (ACPR) improvement for a PA with memoryless predistortion linearizer with respect to the memory effects. Using the input and output complex envelope signals of PA, the ACPR degradation due to memory effects is analytically extracted. A 170 W PEP LDMOS PA is measured and its ACPR performance degradation due to memory effects is analyzed using a memoryless predistortion linearizer.
Key concepts: Predistortion, Linearizer, Adjacent channel power ratio, Amplifier, Lookup table, Electronic engineering, Power (physics), Computer science