Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs

The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combine improvements on algorithm and logic level. To reduce the power consumption of dynamic logic, a method for using single-rail structures is presented including a new scheme to realize inverting logic functions. It is shown that such structure is most efficient when redundant number systems are utilized. These self-timed logic is integrated in a global clock system using the Asynchronous Chain True Single Phase Clock (AC-TSPC) logic resulting in a latch-free structure. Comparisons with other logic styles show the achievement potential. First simulations for a horizontal redundant adder slice show area and power savings of 40% and 30% compared to complementary Domino logic.