Modeling tools built upon the HDL foundation

Hardware description languages, mainly Verilog and VHDL including their analog and mixed-signal extensions, represent a significant investment by the electronic design automation community. Hardware description language technology promises productivity advances such as a medium for intellectual property exchange, model portability, model productivity, greater design collaboration, top-down design for AMS, AMS synthesis, and richer mixed-level, mixed-signal simulation for improved simulation throughput. Modeling tools represent a step toward completion of the dwelling the EDA community seeks to build upon the hardware description language foundation. One such environment of tools is described in this tutorial on Paragon. Paragon is described and demonstrated on both behavioral models using multiple HDLs and compact device modeling applications involving Verilog-A primarily.