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An ultra low voltage ultra high gain CMOS LNA using forward body biasing technique

Ehsan Kargaran, Ghazal Nabovati, Mohammad Reza Baghbanmanesh, Khalil Mafinezhad, Hooman Nabovati

Open publisher page 9 citations

Abstract

A fully integrated 1.5 GHz low noise amplifier suitable for ultra-low voltage applications is designed and simulated in a standard 0.18µm CMOS technology. Using the folded cascode topology and forward body biasing technique, the proposed LNA works at a very low supply voltage and low power consumption. The proposed LNA has a power gain (S21) of 22 dB with a noise figure of 1.9 dB, while consuming 2.5mW dc power with an ultra low supply voltage of 0.5 V.

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What this paper is about

A fully integrated 1.5 GHz low noise amplifier suitable for ultra-low voltage applications is designed and simulated in a standard 0.18µm CMOS technology. Using the folded cascode topology and forward body biasing technique, the proposed LNA works at a very low supply voltage and low power consumption. The proposed LNA has a power gain (S21) of 22 dB with a noise figure of 1.9 dB, while consuming 2.5mW dc power with an ultra low supply voltage of 0.5 V.

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OpenAlex reports 9 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

A fully integrated 1.5 GHz low noise amplifier suitable for ultra-low voltage applications is designed and simulated in a standard 0.18µm CMOS technology. Using the folded cascode topology and forward body biasing technique, the proposed LNA works at a very low supply voltage and low power consumption. The proposed LNA has a power gain (S21) of 22 dB with a noise figure of 1.9 dB, while consuming 2.5mW dc power with an ultra low supply voltage of 0.5 V.

Key concepts: CMOS, Cascode, Biasing, Low voltage, Low-noise amplifier, Ultra low power, Electrical engineering, Noise figure

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