Design of FPGA based on linear array CCD driver circuit
Tiexi Xu, Xianming Xiong, Mingjin Li
Abstract
Tiexi Xu, Xianming Xiong, Mingjin Li
Abstract
Traditional CCD driver circuit is very difficult to satisfy the existing high speed CCD device application due to its complexity and poor anti-interference capability. Besides it's not easy to debug, and its speed and function are limited. In this paper, an FPGA-based on design of linear array CCD device's driver circuit using Toshiba Corporation's TCD1703C is proposed. Firstly, the principle and timing of the TCD1703C are introduced. Then the driving circuit based on Altera Corporation's Cyclone II series EP2C8T144C8 is designed with Verilog HDL. In the simulation with ModelSim SE, it shows that the design meets the timing requirements of the TCD1703C. Lastly, experiment results demonstrate that the result of the CCD outputs can satisfy the existing application request. This design method has the advantages of simplicity of the circuit, high reliability, conveniently debugging and update. All these merits will accelerate the pace of research and development.
OpenAlex reports 10 citations for this work. Citation counts describe recorded attention and do not establish research quality.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
Traditional CCD driver circuit is very difficult to satisfy the existing high speed CCD device application due to its complexity and poor anti-interference capability. Besides it's not easy to debug, and its speed and function are limited. In this paper, an FPGA-based on design of linear array CCD device's driver circuit using Toshiba Corporation's TCD1703C is proposed. Firstly, the principle and timing of the TCD1703C are introduced. Then the driving circuit based on Altera Corporation's Cyclone II series EP2C8T144C8 is designed with Verilog HDL. In the simulation with ModelSim SE, it shows that the design meets the timing requirements of the TCD1703C. Lastly, experiment results demonstrate that the result of the CCD outputs can satisfy the existing application request. This design method has the advantages of simplicity of the circuit, high reliability, conveniently debugging and update. All these merits will accelerate the pace of research and development.
Key concepts: ModelSim, Field-programmable gate array, Computer science, Debugging, Verilog, Breadboard, Reliability (semiconductor), Circuit design