A domain-specific cell based ASIC design methodology for digital signal processing applications

This paper proposes an innovative domain-specific cell based ASIC design flow to narrow the performance gap be-tween the full custom ASIC design method and conventional standard-cell based ASIC design method. The flow can im-prove the design performance and still preserve the effi-ciency of the standard ASIC design flow. Targeting on digi-tal signal processing applications, a domain-specific cell li-brary is provided to augment of standard cell libraries. Ex-perimental results of designing macros such as FFT, FIR etc. are shown in the paper. Based on this methodology a 64-tap FFT can achieve up to 24X performance improve-ment, with the Power Delay Area (PDA) criteria, over the conventional designed ASICs. 1.