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2005•Unpublished venueRequires access

The evolution of DSP architectures: towards parallelism exploitation

R. Sernec, Matej Zajc, J.F. Tasič

Open publisher page 1 citations

Abstract

This paper presents a path of parallelism exploitation in commercial programmable DSP processors. DSP processors have gained in their complexity and have adopted some very sophisticated parallelism extraction techniques, namely very long instruction word (VLIW) and SIMD designs. The intention is to show a development path of digital signal processors (DSP) and focuses on their features that allow parallel processing of algorithms.

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What this paper is about

This paper presents a path of parallelism exploitation in commercial programmable DSP processors. DSP processors have gained in their complexity and have adopted some very sophisticated parallelism extraction techniques, namely very long instruction word (VLIW) and SIMD designs. The intention is to show a development path of digital signal processors (DSP) and focuses on their features that allow parallel processing of algorithms.

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OpenAlex reports 1 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

This paper presents a path of parallelism exploitation in commercial programmable DSP processors. DSP processors have gained in their complexity and have adopted some very sophisticated parallelism extraction techniques, namely very long instruction word (VLIW) and SIMD designs. The intention is to show a development path of digital signal processors (DSP) and focuses on their features that allow parallel processing of algorithms.

Key concepts: Very long instruction word, Digital signal processing, Computer science, Parallelism (grammar), SIMD, Parallel computing, Instruction-level parallelism, Path (computing)

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