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Grid Memory Service Architecture for High Performance Computing

Lei Li, Siyuan Liu, Mingyu Chen, Jianping Fan

Open publisher page 3 citations

Abstract

Increasing network and data intensive applications demand more to computing and memory capacity. But tight coupling between CPU and memory makes it hard to share memory components, resulting in difficulty to improve system performance and reduce system cost. Furthermore, nowadays memory architecture cannot adapt "small computing, big memory" feature of application. Supporting by optical interconnect and reconfigurable technology, memory can be separated with CPU and gathered into memory server to provide grid service. This paper proposed a grid memory service (GMS) architecture, which is implemented by memory box. Design of GMS architecture focuses on high speed, high volume, dynamically shared, high scalability, flexibility and autonomy. Programming model and uniform access interface is designed to satisfy vary clients and application. A serial, packet switching based optical interconnect GMIP is designed to obtain high speed and high scalability. With rich and cheap embedded processor and control logic in memory box, distributed intelligent memory is implemented, including distributed processing, multi-level memory management and active memory. A prototype is implemented as verification platform and the test result illustrates low access latency of memory box, improved performance than disk, and good effect of active memory.

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What this paper is about

Increasing network and data intensive applications demand more to computing and memory capacity. But tight coupling between CPU and memory makes it hard to share memory components, resulting in difficulty to improve system performance and reduce system cost. Furthermore, nowadays memory architecture cannot adapt "small computing, big memory" feature of application. Supporting by optical interconnect and reconfigurable technology, memory can be separated with CPU and gathered into memory server to provide grid service. This paper proposed a grid memory service (GMS) architecture, which is implemented by memory box. Design of GMS architecture focuses on high speed, high volume, dynamically shared, high scalability, flexibility and autonomy. Programming model and uniform access interface is designed to satisfy vary clients and application. A serial, packet switching based optical interconnect GMIP is designed to obtain high speed and high scalability. With rich and cheap embedded processor and control logic in memory box, distributed intelligent memory is implemented, including distributed processing, multi-level memory management and active memory. A prototype is implemented as verification platform and the test result illustrates low access latency of memory box, improved performance than disk, and good effect of active memory.

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Available abstract

Increasing network and data intensive applications demand more to computing and memory capacity. But tight coupling between CPU and memory makes it hard to share memory components, resulting in difficulty to improve system performance and reduce system cost. Furthermore, nowadays memory architecture cannot adapt "small computing, big memory" feature of application. Supporting by optical interconnect and reconfigurable technology, memory can be separated with CPU and gathered into memory server to provide grid service. This paper proposed a grid memory service (GMS) architecture, which is implemented by memory box. Design of GMS architecture focuses on high speed, high volume, dynamically shared, high scalability, flexibility and autonomy. Programming model and uniform access interface is designed to satisfy vary clients and application. A serial, packet switching based optical interconnect GMIP is designed to obtain high speed and high scalability. With rich and cheap embedded processor and control logic in memory box, distributed intelligent memory is implemented, including distributed processing, multi-level memory management and active memory. A prototype is implemented as verification platform and the test result illustrates low access latency of memory box, improved performance than disk, and good effect of active memory.

Key concepts: Computer science, Uniform memory access, Flat memory model, Interleaved memory, Computing with Memory, Memory map, Registered memory, Cache-only memory architecture

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