1996•ITC-CSCC :International Technical Conference on Circuits Systems, Computers and CommunicationsRequires access

VLSI Architecture for Very Low Bitrate Video Encoder Core

Koji Miyanohana, Gen Fujita, Takao Onoye, Isao Shirakawa, Nariyoshi Yamai

Open publisher page 0 citations

Abstract

This record does not include an abstract. Use the full-text link above if available.

About this research paper

What this paper is about

An abstract is not available in the OpenAlex record for this paper.

Why it matters

A significance statement is not available in the OpenAlex record.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Key concepts: Computer science, Encoder, Very-large-scale integration, Architecture, Codec, Computer architecture, Core (optical fiber), Computer hardware

Back to paper search Browse research topics Original source

VLSI Architecture for Very Low Bitrate Video Encoder Core — Research Paper | ScholarLens