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An Error-Correcting Line Encoding ASIC for a HEP Rad-Hard Multi-GigaBit Optical Link

Giulia Papotti

Open publisher page 5 citations

Abstract

This paper presents an ASIC implementing the line encoding scheme to be used in the GBT system, a multi-gigabit optical link designed for use in a High Energy Physics environment. A general overview of issues specific to optical links placed in radiation environments is given, and the required properties of the line encoding discussed. A scheme that preserves the DC-balance of the line and allows forward error correction is proposed. It is implemented through the concatenation of scrambling, Reed-Solomon error-correction and addition of an 8-bit DC-balanced header. The proposed scheme has been implemented in a fully digital chip fabricated in a 0.13μm CMOS technology. Implementation details and test and simulation results are given.

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What this paper is about

This paper presents an ASIC implementing the line encoding scheme to be used in the GBT system, a multi-gigabit optical link designed for use in a High Energy Physics environment. A general overview of issues specific to optical links placed in radiation environments is given, and the required properties of the line encoding discussed. A scheme that preserves the DC-balance of the line and allows forward error correction is proposed. It is implemented through the concatenation of scrambling, Reed-Solomon error-correction and addition of an 8-bit DC-balanced header. The proposed scheme has been implemented in a fully digital chip fabricated in a 0.13μm CMOS technology. Implementation details and test and simulation results are given.

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OpenAlex reports 5 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

This paper presents an ASIC implementing the line encoding scheme to be used in the GBT system, a multi-gigabit optical link designed for use in a High Energy Physics environment. A general overview of issues specific to optical links placed in radiation environments is given, and the required properties of the line encoding discussed. A scheme that preserves the DC-balance of the line and allows forward error correction is proposed. It is implemented through the concatenation of scrambling, Reed-Solomon error-correction and addition of an 8-bit DC-balanced header. The proposed scheme has been implemented in a fully digital chip fabricated in a 0.13μm CMOS technology. Implementation details and test and simulation results are given.

Key concepts: Computer science, Gigabit, Header, Application-specific integrated circuit, Encoding (memory), Error detection and correction, Scrambling, Concatenation (mathematics)

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