A DSP peripheral design for three-level inverter space vector PWM modulations

Presently available motion drive digital signal processors (DSP) are all equipped with PWM modulation peripherals supporting only two-level power inverter topology. There is a considerable interfacing gap between the DSP controller and the inverter gate driver circuits of multi-level power inverter topologies. This paper explores the possibility of designing a new, standard DSP peripheral for three-level inverter space vector PWM modulation via a CPLD prototype, extending the conventional two-level PWM peripheral to embrace three-level PWM modulation capability. General design perspectives are given and experimental results are presented to validate the new peripheral design.