Datapath intensive ASIC design-synthesis from VHDL

Comprehensive design space exploration is possible by means of synthesising VHDL datapaths into compiled silicon. A typical flow would include features such as design partitioning of ASIC VHDL descriptions into datapath and random logic blocks, a datapath library comprising a rich set of highly optimised layout components (like adders, multipliers, ALUs, memory storage elements), resource selection and sharing of datapath library components, boolean and performance optimisation, as well as user defined synthesis constraints and directives applied to the VHDL source. Mapping directly to datapath components, synthesis runtimes are dramatically reduced, while at the same time compiled components offer improvements in speed, area and power as well as uniform clock delays. The author focuses on the ASIC synthesis flow from VHDL, the impact of VHDL coding styles and the enabling EDA tool features.