Silicon technology directions in the nanoelectronics era
M.R. Pinto
Abstract
M.R. Pinto
Abstract
For decades the scalability of MOS technology has fostered continual improvements in almost every dimension of electronic products. However at /spl sim/130nm, VLSI has neared a variety of limits threatening compromises, and the industry has returned to a state more like the 1970s where new directions in materials, processes and devices are being intensively evaluated. However the complexity of the challenge today is many orders of magnitude higher - e.g. controlling atomic thickness over billions of components - while economic pressures, both on R&D as well as time to yield, are driving a new industry landscape. This presentation explores key technology challenges and reviews main industry directions - many times across traditional R&D boundaries - that enables the pervasive growth in application content promised by the nanoelectronics era.
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For decades the scalability of MOS technology has fostered continual improvements in almost every dimension of electronic products. However at /spl sim/130nm, VLSI has neared a variety of limits threatening compromises, and the industry has returned to a state more like the 1970s where new directions in materials, processes and devices are being intensively evaluated. However the complexity of the challenge today is many orders of magnitude higher - e.g. controlling atomic thickness over billions of components - while economic pressures, both on R&D as well as time to yield, are driving a new industry landscape. This presentation explores key technology challenges and reviews main industry directions - many times across traditional R&D boundaries - that enables the pervasive growth in application content promised by the nanoelectronics era.
Key concepts: Nanoelectronics, Scalability, Moore's law, Variety (cybernetics), Dimension (graph theory), Yield (engineering), Nanotechnology, Key (lock)