Efficient line buffer instruction cache scheme with prefetch

Cache is an important component of modern processor. On chip instruction cache can comprise one third of CPU power. So both the energy efficiency and performance should be concerned when designing processors. Line buffer cache architecture, which adds a line size buffer between Level 1 cache and IU (integer unit), has the advantage of low energy consumption. But the scheme decreases the performance by about 20%. Prefetch is a useful scheme to improve the performance of processor. In this paper, based on the line buffer cache architecture, the prefetch scheme is introduced in to prefetch the request instructions from Level 1 cache to the line buffer in the hope of improving the processor performance without power consumption increasing significantly. The Leon 2 VHDL model is used as the environment to fulfill the method. The results show that the proposed architecture improves the performance by 12.4% with 4.9% power consumption increasing compared with line buffer cache.