1999•IEEE Transactions on Circuits and Systems II Analog and Digital Signal ProcessingRequires access

Effect of switch resistance on the SC integrator settling time

U. Chilakapari, Terri S. Fiez

Abstract

Using general feedback theory, a model is developed for the switched-capacitor integrator. This model is then used to analyze the effects of sampling and feedback switch resistances on the integrator settling time. If the frequency corresponding to the sampling time constant is less than five times the frequency of the second pole of the amplifier, the integrator settling time will be degraded. The feedback switch resistance has little effect on the integrator settling time for switch resistances up to 50 k/spl Omega/.

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Key concepts: Integrator, Settling time, Passive integrator circuit, Settling, Op amp integrator, Control theory (sociology), Time constant, Integrating ADC