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Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG

Hideyuki Ichihara, Tomoo Inoue

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Abstract

This paper proposes a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just combinational test pattern generation algorithm for single stuck-at faults

About this research paper

What this paper is about

This paper proposes a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just combinational test pattern generation algorithm for single stuck-at faults

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OpenAlex reports 3 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

This paper proposes a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just combinational test pattern generation algorithm for single stuck-at faults

Key concepts: Automatic test pattern generation, Combinational logic, Sequential logic, Stuck-at fault, Fault coverage, Algorithm, Computer science, Electronic circuit

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