Compiler-Based Register Name Adjustment for Low-Power Embedded Processors

We present an algorithm for compiler-driven register name adjustment with the main goal of power minimization on instruction fetch and register file access. In most instruction set architecture (ISA) designs, the register fields reside in fixed positions within the instruction encoding, hence forming streams of indices on the instruction bus and to the register file address decoder. The number of bit transitions in these streams greatly determines the power consumption on the address bus and the register file decoder. While general-purpose registers are semantically indistinguishable and hence interchangeable, the particular register indices do have a direct impact on power consumption. The algorithms presented in this paper address this power minimization problem by reassigning/encoding the registers so that the bit transitions within the register index streams are minimized.