Comparison of ultra-low-power and static CMOS full adders in 0.15 µm FD SOI CMOS

Ultra-low-power and static CMOS full adders are implemented in a 0.15 mum FD SOI CMOS technology with 1.5 V supply. The power consumption of ultra-low-power full adder is shown to be half that of static CMOS. These results are confirmed by both measurements and SPICE simulations in different corners of operation.