Very fast methodology for the simulation of CMOS combinatorial circuits including noise

The noise immunity of digital CMOS designs is considered as one of the reasons for its huge success. However, low power design has become necessary to cope with the power demand and shrinking device sizes. At the same time, the electromagnetic compatibility requirements have become more and more stringent, with the result that Electromagnetic Interference (EMI) can be considered as a serious noise source for future digital designs. In this paper, the effects of EMI on digital combinational logic is discussed, and a model for the immunity of digital circuits is proposed.