A fully matched N-way doherty amplifier with optimized linearity

This paper presents a new fully matched N-way Doherty amplifier. The basic principles of operation and important features are described. For the experimental verification, 2.14-GHz Doherty amplifiers having two-, three-, and four-way structures are implemented using silicon LDMOSFETs and tested using down-link WCDMA signal. The linearity performances of the two-, three-, and four-way Doherty amplifiers are optimized for better efficiency versus linearity by a bias adjustment of the peaking amplifiers. For simultaneously improving the efficiency and linearity to achieve maximum efficiency versus linearity, the gate biases of the peaking amplifiers for the N-way Doherty amplifier are optimized. As a result, the efficiency versus linearity characteristics are drastically improved by N-way extension of the Doherty amplifier.