2008Unpublished venueRequires access

Efficient dynamic heap allocation of scratch-pad memory

Ross McIlroy, Peter Dickman, Joe Sventek

Open publisher page 49 citations

Abstract

An increasing number of processor architectures support scratch-pad memory - software managed on-chip memory. Scratch-pad memory provides low latency data storage, like on-chip caches, but under explicit software control. The simple design and predictable nature of scratchpad memories has seen them incorporated into a number of embedded and real-time system processors. They are also employed by multi-core architectures to isolate processor core local data and act as low latency inter-core shared memory.

About this research paper

What this paper is about

An increasing number of processor architectures support scratch-pad memory - software managed on-chip memory. Scratch-pad memory provides low latency data storage, like on-chip caches, but under explicit software control. The simple design and predictable nature of scratchpad memories has seen them incorporated into a number of embedded and real-time system processors. They are also employed by multi-core architectures to isolate processor core local data and act as low latency inter-core shared memory.

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OpenAlex reports 49 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

An increasing number of processor architectures support scratch-pad memory - software managed on-chip memory. Scratch-pad memory provides low latency data storage, like on-chip caches, but under explicit software control. The simple design and predictable nature of scratchpad memories has seen them incorporated into a number of embedded and real-time system processors. They are also employed by multi-core architectures to isolate processor core local data and act as low latency inter-core shared memory.

Key concepts: Computer science, Heap (data structure), Parallel computing, Interleaved memory, Embedded system, Latency (audio), Software, Non-uniform memory access

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