Reducing the number of instructions

The purpose of this article is to reduce the number of instructions while executing in processor. We analyse memory address dependent instructions and eliminate the address generation processing if the address was previously calculated. For standard RISC, VLIW and in-order superscalar processor we introduce a solution where the RMI (Reduction of Memory Instructions) algorithm is performed in the compile stage and address dependent instructions do not enter the processor at all. For out-of-order superscalar processors we introduce two solutions, the first one when these instructions are not issued at all and the second solution when these instructions are issued only in a reservation station without execution unit. All these solutions improve the behaviour of the processor for at least 10% since the processor does not execute these instructions.